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  mos integrated circuits pd63335 stereo sound codec data sheet 2000 ? the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. the mark shows major revised points. document no. s15003ej6v0ds00 (6th edition) date published february 2002 n cp(k) printed in japan description the pd63335 is a stereo sound codec lsi that enables full-duplex communications and features two channels each of on-chip 16-bit adc and dac circuits for mutual conversion between digital signals and audio analog signals (having a maximum s ignal bandwidth of 20 khz). the analog signal input block enables four pairs of stereo signals plus three monaural signals to be output from the output stage's internal mixing circuit, which can then be multiplexed and input to the adc. one type of monaural signal can be selected from two external pins via a selector as a monaural signal connected to an internal microphone amplifier (mic amp), with selectable gain of 0 db or 20 db. the analog signal output block enables mixed output of analog signals output by the dac, four pairs of stereo analog signals, and an output signal from the mic amp, and the volume of each signal can be controlled independently before mixing. the digital audio signal i/o block supports an audio-type serial interface (two's complement). in addition, a clocked serial interface (csi) can be used for direct connection to a general-purpose microcontroller for access to internal registers such as for volume control. features ? two channels each of over sample ? type adc and dac ? adc snr = 85 db typ.  dac snr = 90 db typ. ? adc and dac digital filter characteristics  pass band ripple: 0.1 db (0 to 0.4 f s ) for adc and dac  stop band att enuation: ? 74 db (0.6 f s ) or above for adc and dac ? sampling frequency (f s ): 0.4 to 48 khz  division rate from master clock can be set to 3072, 1536, 768, or 512 ? analog input block includes a multiplexer and analog output block includes a mixing circuit ? low-noise monaural mic amp is on chip ? on-chip reference voltage power supply (1.4 v (typ.)) ? low supply voltage operation: dv dd = 3.3 v, av dd = 3.3 v ? support for power down mode in each internal block ? operating ambient temperature: ? 40 to +85 c applications  speech recognition systems, including car navigation systems  electronic toys with speech/audio i/o functions ordering information part number package pd63335ga-9eu 48-pin plastic tqfp (fine pitch) (7 7)
data sheet s15003ej6v0ds 2 pd63335 block diagram remark the ms and mix blocks are selectors. ? 6 db mixer mc20 0 db/ 20 db multiplexer multiplexer mix mixer mixer mixer mixer ms so si lrclk mswdt msrdt msclk reset xtl_in xtl_out bit_clk mic2 mic1 in2l in1l in4l in5 in3l stereo mix/l mono mix stereo mix/r dac mono in1r in6 mono_out in3r in4r outl dacl dacr outr in2r digital data interface digital command interface analog output pins analog input pins in4r in3r in2r in1r mic mono mix in5 in1r in2r in3r in4r stereo mix/r in5 in6 mic mic in4l in3l in2l in1l in5 mono mix in1l in2l mic stereo mix/l in3l in4l ? 6 db mixer digital filter i/o interface interpolator interpolator dac dac decimator decimator adc adc loop-back (test mode)
data sheet s15003ej6v0ds 3 pd63335 pin configuration (top view) 48-pin plastic tqfp (fine pitch) (7 7) ? pd63335ga-9eu dv dd3 msrdt mswdt test2 test1 av ss2 msclk dacr nc av dd2 mono_out dacl in5 in3l in3r in2r in1l in1_gnd in2l in1r mic1 in4l in4r mic2 dv dd1 xtl_in xtl_out si bit_clk dv ss2 dv ss1 so dv dd2 reset in6 lrclk 36 35 34 32 31 30 33 29 28 26 25 27 outr outl nc nc nc afilt2 nc afilt1 nc av ss1 av dd1 vref 1 2 3 5 6 7 4 8 9 11 12 10 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24
data sheet s15003ej6v0ds 4 pd63335 pin functions (1/2) pin no. symbol i/o function 1dv dd1 ? digital power supply 2 xtl_in i crystal resonator connection pin/external master clock input (see 1.3 clock ) 3 xtl_out o crystal resonator connection pin. leave this pin open when using an external master clock. 4dv ss1 ? digital ground 5si i data input for serial data interface note 6 bit_clk i/o bit sync clock for serial data interface note 7dv ss2 ? digital ground 8 so o data output for serial data interface 9dv dd2 ? digital power supply 10 lrclk i/o frame sync clock for serial data interface note 11 _______ reset i reset signal input. sets reset mode when low. 12 in6 i analog audio monaural input 6 13 in5 i analog audio monaural input 5 14 in3l i analog audio input 3, l channel 15 in3r i analog audio input 3, r channel 16 in2l i analog audio input 2, l channel 17 in2r i analog audio input 2, r channel 18 in1l i analog audio input 1, l channel 19 in1_gnd ? ac ground pin for in1. generally connect to av ss via a 1 f capacitor. 20 in1r i analog audio input 1, r channel 21 mic1 i mic input 1 22 mic2 i mic input 2 23 in4l i analog audio input 4, l channel 24 in4r i analog audio input 4, r channel 25 av dd1 ? analog power supply 26 av ss1 ? analog ground 27 vref ? reference voltage output for connecting bypass capacitor 28 nc ? not used. leave this pin open. 29 afilt1 ? adc l channel anti alias filter pin 30 afilt2 ? adc r channel anti alias filter pin 31 nc ? not used. leave this pin open. 32 nc ? not used. leave this pin open. 33 nc ? not used. leave this pin open. 34 nc ? not used. leave this pin open. note the si, bit_clk, and lrclk pins are neither pulled up nor pulled down within the lsi. since malfunction may occur if these pins are somehow set to high impedance, pull-up or pull-down should be performed externally, via a resistor.
data sheet s15003ej6v0ds 5 pd63335 (2/2) pin no. symbol i/o function 35 outl o analog audio output pin, l channel 36 outr o analog audio output pin, r channel 37 mono_out o analog audio monaural output 38 av dd2 ? analog power supply 39 dacl o analog dac signal output, l channel 40 nc ? not used. leave this pin open. 41 dacr o analog dac signal output, r channel 42 av ss2 ? analog ground 43 test1 ? test pin for ic sorting. leave this pin open. 44 test2 ? test pin for ic sorting. leave this pin open. 45 msclk i sync clock input for serial command interface 46 mswdt i input for serial command interface 47 msrdt o output for serial command interface 48 dv dd3 ? digital power supply
data sheet s15003ej6v0ds 6 pd63335 contents 1. description of functions ................................................................................................... ........................ 8 1.1 analog input block .......................................................................................................... .............................. 8 1.2 analog output block ......................................................................................................... ............................ 8 1.3 clock ....................................................................................................................... ........................................ 8 1.3.1 switching external master clock frequency ................................................................................. .9 1.4 reset ....................................................................................................................... ...................................... 10 1.5 pin to connect noise-reducing capacitor..................................................................................... ........... 10 1.6 digital interfaces.......................................................................................................... ................................ 11 1.6.1 serial command interface .................................................................................................. ........... 11 1.6.2 serial data interface..................................................................................................... .................. 12 1.6.3 data format of fsdf2:fsdf1:fsdf0:lrclks = 0:0:0:0 ............................................................ 16 1.6.4 data format of fsdf2:fsdf1:fsdf0:lrclks = 0:0:0:1 ............................................................ 16 1.6.5 data format of fsdf2:fsdf1:fsdf0:lrclks = 0:0:1:0 ............................................................ 17 1.6.6 data format of fsdf2:fsdf1:fsdf0:lrclks = 0:0:1:1 ............................................................ 17 1.6.7 data format of fsdf2:fsdf1:fsdf0:lrclks = 0:1:0:0 ............................................................ 18 1.6.8 data format of fsdf2:fsdf1:fsdf0:lrclks = 0:1:0:1 ............................................................ 18 1.6.9 data format of fsdf2:fsdf1:fsdf0:lrclks = 0:1:1:0 ............................................................ 19 1.6.10 data format of fsdf2:fsdf1:fsdf0:lrclks = 0:1:1:1 ............................................................ 19 1.6.11 data format of fsdf2:fsdf1:fsdf0:lrclks = 1:0:0:0 ............................................................ 20 1.6.12 data format of fsdf2:fsdf1:fsdf0:lrclks = 1:0:0:1 ............................................................ 20 1.6.13 data format of fsdf2:fsdf1:fsdf0:lrclks = 1:0:1:0 ............................................................ 21 1.6.14 data format of fsdf2:fsdf1:fsdf0:lrclks = 1:0:1:1 ............................................................ 21 1.6.15 data format of fsdf2:fsdf1:fsdf0:lrclks = 1:1:0:0 ............................................................ 22 1.6.16 data format of fsdf2:fsdf1:fsdf0:lrclks = 1:1:0:1 ............................................................ 22 1.6.17 data format of fsdf2:fsdf1:fsdf0:lrclks = 1:1:1:0 (initial value) ..................................... 23 1.6.18 data format of fsdf2:fsdf1:fsdf0:lrclks = 1:1:1:1 ............................................................ 23 1.7 usage precautions ........................................................................................................... ........................... 23 2. registers.................................................................................................................... ....................................... 24 2.1 individual registers........................................................................................................ ............................. 25 2.1.1 serial command interface check bit (sick)................................................................................. 25 2.1.2 reset/clock status register (00h)......................................................................................... ......... 25 2.1.3 interface/timing register (01h) ........................................................................................... ........... 26 2.1.4 input select register (02h) ............................................................................................... .............. 27 2.1.5 adc input gain registers (03h, 04h) ....................................................................................... ...... 28 2.1.6 in1 volume registers (05h, 06h)........................................................................................... ......... 29 2.1.7 in2 volume registers (07h, 08h)........................................................................................... ......... 30 2.1.8 in3 volume registers (09h, 0ah) ........................................................................................... ........ 31 2.1.9 in4 volume registers (0bh, 0ch)........................................................................................... ........ 32 2.1.10 in5 volume register (0dh) ................................................................................................ ............. 33 2.1.11 mic volume register (0eh)................................................................................................ ............. 34 2.1.12 in6 volume register (0fh)................................................................................................ .............. 35 2.1.13 dac volume registers (10h, 11h).......................................................................................... ........ 36 2.1.14 out master volume registers (12h, 13h) ................................................................................... .. 37
data sheet s15003ej6v0ds 7 pd63335 2.1.15 dac master volume registers (14h, 15h)................................................................................... ...38 2.1.16 mono output master volume register (16h) ................................................................................3 9 2.1.17 path select register (17h) ............................................................................................... ................40 2.1.18 power down control register (18h)........................................................................................ ........41 2.1.19 warm reset register (7fh) ................................................................................................ ..............43 3. electrical specifications................................................................................................... .......................44 4. application circuit example ................................................................................................ ....................51 5. recommended land pattern................................................................................................... ..................52 6. package drawing ............................................................................................................. ..............................53 7. recommended soldering conditions........................................................................................... .........54
data sheet s15003ej6v0ds 8 pd63335 1. description of functions 1.1 analog input block the pd63335 features an on-chip two-channel adc, which can convert analog signals selected by the multiplexer at the previous stage and input via the analog input pin to digital signals. an amplifier is configured between the adc and multiplexer, and the input gain can be set in a range from 0 db to 22.5 db. the multiplexer receives signals that are input from the analog output block?s mixer circuit, and four-channel stereo signals, two monaural signals, and a monaural mic input signal (selected from two input pins) from the analog input pins. the in1 input has a dedicated ac ground pin for canceling common-mode noise. use of the in1_gnd pin enables connections to output pins that have a ground line, such as a cd audio output pin, via a 4.7 f capacitor. if not using in1_gnd, connect to a ground via a 1 f capacitor (see figure 1-1 ). figure 1-1. connection example when not using in1_gnd 1.2 analog output block the analog output block includes two stereo output amplifiers, a monaural output amplifier, and a mixer circuit. the mixer circuit can be used to mix not only stereo analog signals from the dac but also four pairs of stereo signals (in1 to in4), one monaural signal, and one mic input signal (selected from two input pins). the analog signals from the dac output can be connected to the mixer circuit or dac l/r output via volume circuits. monaural mixed signals to the monaural output selector (mix) are the sum of the l channel/r channel mixer circuit output to which ?6 db of gain adjustment is applied within the lsi. 1.3 clock the pd63335 features an on-chip clock generator. the pd63335?s master clock can be generated if a crystal resonator is connected via the xtl_in or xtl_out pin. the on-chip clock generator can be used only at the 24.576 mhz setting. in addition, an external master clock can be input to the on-chip clock generator. in such cases, input the clock signal directly to the xtl_in pin and leave the xtl_out pin open. in this case, the recommended frequency range of the external master clock is from 1.024 mhz to 24.576 mhz. pd63335 1 f in1_gnd
data sheet s15003ej6v0ds 9 pd63335 1.3.1 switching external master clock frequency to switch the external master clock frequency during adc and dac operation, use the following procedure. (1) when using the master mode (lrclk, bit_clk generated internally) <1> set the dac volume register (10h, 11h) and the dac master volume register (14h, 15h) to mute note 1 . <2> switch the external master clock frequency. <3> set the lrclk/bit_clk operation mode (if there is a change) (use the reset/clock status register (00h)). <4> set the audio format (if there is a change) (use the interface/timing register (01h)). <5> set the dac volume register (10h, 11h) and dac master volume register (14h, 15h) note 2 notes 1. the instant that the external master clock frequency is switched, noise may occur. for this reason, before switching the external master clock, set the volume for the dac output to mute. 2. to prevent popping noises, after switching the external master clock frequency and following the lapse of an interval of time sufficient for three or more lrclk cycles to be supplied, cancel the mute setting of the volume for the dac output. also handle the adc output data (so) as valid data once the same interval of time has elapsed. (2) when using the slave mode (lrclk, bit_clk supplied from external) <1> set the dac volume register (10h, 11h) and the dac master volume register (14h, 15h) to mute note 1 . <2> power down the adc and dac (use the power down control register (18h)). <3> switch the external master clock, lrclk, bit_clk frequency. <4> set the lrclk/bit_clk operation mode (if there is a change) (use the reset/clock status register (00h)). <5> set the audio format (if there is a change) (use the interface/timing register (01h)). <6> cancel adc, dac power down (use the power down control register (18h)). <7> set the dac volume register (10h, 11h) and dac master volume register (14h, 15h) note 2 . notes 1. immediately after the adc and dac are powered down, noise may occur in the adc and dac outputs. for this reason, before powering down the adc and dac, set the volume for the dac output to mute. 2. to prevent popping noises, after canceling power down and following the lapse of an interval of time sufficient for three or more lrclk cycles to be supplied, cancel the mute setting of the volume for the dac output. also handle the adc output data (so) as valid data once the same interval of time has elapsed.
data sheet s15003ej6v0ds 10 pd63335 1.4 reset the pd63335 features three reset modes. (1) cold reset cold reset is controlled by input signals via the _______ reset pin, and is used to initialize the pd63335. registers are reset to their initial values. (2) warm reset a warm reset is used to reset the digital command interface for any reason. when ffh is written to the warm reset register (7fh), the pd63335 performs a warm reset. register values are retained during a warm reset. (3) register reset this initializes the pd63335?s internal registers. all registers are reset, except for the following registers. ? reset/clock status register (00h) ? interface/timing register (01h) ? power down control register (18h) 1.5 pin to connect noise-reducing capacitor pin 27 is a reference voltage pin that is used to connect to a bypass capacitor for stabilizing the internal reference voltage. connect the bypass capacitor as shown in the figure below. figure 1-2. example of bypass capacitor connection pins 29 and 30 are used to connect capacitors for the adc?s anti alias filter. connect the capacitor as shown in the figure below. figure 1-3. example of capacitor connection for anti alias filter pd63335 270 pf afilt1 270 pf afilt2 pd63335 0.1 f tantalum capacitor 4.7 f + ceramic capacitor vref
data sheet s15003ej6v0ds 11 pd63335 1.6 digital interfaces the pd63335 uses two different interfaces to connect to an external host processor (such as a cpu or sound controller). one is the serial command interface that controls the pd63335, and the other is the serial data interface that is used for data input and output. figure 1-4. digital interfaces 1.6.1 serial command interface when accessing the pd63335 from an external host processor, use the clocked serial interface (msclk, mswdt, msrdt). transfer of addresses begins in sync with the rising edge of msclk, immediately after the reset signal goes from low level to high level. addresses consist of eight bits, of which bit 7 indicates the read/write attribute for access. when a ?1? is transferred to bit 7 in the address, a read operation is performed. after an address is input via the mswdt pin, the contents of the corresponding register are output via the msrdt pin. when a ?0? is transferred to bit 7 in the address, a write operation is performed. once the address is sent from the host processor, 8-bit data is written. the pd63335 uses the data to check for bit drift in the serial command interface so as to ensure accurate control from the host processor. when communication is being performed correctly, the d6 address bit of all the registers except the warm reset register (7fh) is always ?0?, and the d7 and d6 data bits are always ?01?. the d6 data bit (sick) is used to check for the occurrence of bit displacement among the serial command interface bits. for details of the sick bit, refer to 2.1.1 serial command interface check bit (sick) . lrclk bit_clk si so msclk mswdt msrdt pd63335 host processor serial command interface serial data interface msclk reset mswdt (input) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 msrdt (output) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address write data read data
data sheet s15003ej6v0ds 12 pd63335 1.6.2 serial data interface four sampling frequency settings can be made for the pd63335 by setting the rate[1:0] bit in an internal register (00h). registers 00h and 01h can be used to set the polarity of the frame signal (lrclk) and to switch the i/o status of the lrclk and bit_clk signals. some noise may occur when switching the format of the serial data interface during operation. before switching, set the analog output volume to ?mute? (see 2.1.14 to 2.1.16 ). selection of sampling rate (set via rate[1:0] bit in register 00h) rate [1:0] sampling rate in case of f mclk = 24.576 mhz 00 f mclk /3072 (initial value) 8 khz 01 f mclk /1536 16 khz 10 f mclk /768 32 khz 11 f mclk /512 48 khz selection of audio data format (set via fsdf[2:0] bit in register 01h) audio data format (2?s complement, msb first) fsds [2:0] bit clocks per frame pcm input data: si pcm output: so 000 64 left justified left justified 001 64 left justified right justified 010 64 right justified left justified 011 64 right justified right justified 100 48 left justified left justified 101 48 left justified right justified 110 48 right justified left justified 111 32 (initial value) ?? selection of lrclk polarity (set via lrclks bit in register 00h) lrclk level lrclks high level low level 0 l channel (initial value) r channel (initial value) 1 r channel l channel selection of lrclk/bit_clk direction (set via clkios bit in register 00h) clkios lrclk/bit_clk direction 0 input (initial value) 1 output the pd63335 can operate in both master mode (the mode in which the pd63335 outputs lrclk and bit_clk) and slave mode (the mode in which the pd63335 is supplied with lrclk and bit_clk externally). set the registers related to each mode using the recommended procedure below.
data sheet s15003ej6v0ds 13 pd63335 (1) when using the master mode (lrclk, bit_clk generated internally) (a) to start adc, dac operation from the adc, dac power down status (including at power on) <1> set the dac volume register (10h, 11h) and dac master volume register (14h, 15h) to mute note 1 . <2> set the lrclk/bit_clk operation mode (use the reset/clock status register (00h)) note 2 . <3> set the audio format (use the interface/timing register (01h)). <4> cancel adc, dac power down (use the power down control register (18h)). <5> set the dac volume register (10h, 11h) and the dac master volume register (14h, 15h) note 3 . (b) to change the lrclk/bit_clk operation mode setting during adc, dac operation <1> set the dac volume register (10h, 11h) and the dac master volume register (14h, 15h) to mute note 4 . <2> change the lrclk/bit_clk operation mode setting (use the reset/clock status register (00h)). <3> set the audio format (if there is a change) (use the interface/timing register (01h)). <4> set the dac volume register (10h, 11h) and the dac master volume register (14h, 15h) note 5 . notes 1. immediately after canceling adc, dac power down, noise may occur in the adc and dac outputs. for this reason, before canceling power down, set the volume for dac output to mute. (if these volumes are already set to mute, at power on, etc., setting them to mute again is not required.) 2. the lrclk/bit_clk operation mode is set to the slave mode by default. to use it in the master mode, switch the lrclk/bit_clk operation mode to the master mode while the adc and dac are powered down. 3. to prevent popping noises, after canceling power down and following the lapse of an interval of time sufficient for three or more lrclk cycles to be supplied, cancel the mute setting of the volume for the dac output. also handle the adc output data (so) as valid data once the same interval of time has elapsed. 4. immediately after changing the lrclk/bit_clk operation mode, noise may occur in the adc and dac outputs. for this reason, before changing this setting, set the volume for dac output to mute. 5. to prevent popping noises, after changing the lrclk/bit_clk operation mode, following the lapse of an interval of time sufficient for three or more lrclk cycles to be supplied, cancel the mute setting of the volume for the dac output. also handle the adc output data (so) as valid data once the same interval of time has elapsed.
data sheet s15003ej6v0ds 14 pd63335 (2) when using the slave mode (lrclk, bit_clk supplied from external) (a) to start adc, dac operation from the adc, dac power down status (including at power on) <1> set the dac volume register (10h, 11h) and dac master volume register (14h, 15h) to mute note 1 . <2> start supplying the external clock (lrclk, bit_clk) note 2 . <3> set the lrclk/bit_clk operation mode (use the reset/clock status register (00h)). <4> set the audio format (use the interface/timing register (01h)). <5> cancel adc, dac power down (use the power down control register (18h)). <6> set the dac volume register (10h, 11h) and the dac master volume register (14h, 15h) note 3 . (b) to change the lrclk/bit_clk operation mode setting during adc, dac operation <1> set the dac volume register (10h, 11h) and the dac master volume register (14h, 15h) to mute note 4 . <2> switch the external clock (lrclk, bit_clk) note 5 . <3> change the lrclk/bit_clk operation mode setting (use the reset/clock status register (00h)). <4> set the audio format (if there is a change) (use the interface/timing register (01h)). <5> set the dac volume register (10h, 11h) and the dac master volume register (14h, 15h) note 6 . notes 1. immediately after canceling adc, dac power down, noise may occur in the adc and dac outputs. for this reason, before canceling power down, set the volume for dac output to mute. (if these volumes are already set to mute, at power on, etc., setting them to mute again is not required.) 2. start supplying the external clock (lrclk, bit_clk) prior to setting the lrclk/bit_clk operation mode. 3. to prevent popping noises, after canceling power down and following the lapse of an interval of time sufficient for three or more lrclk cycles to be supplied, cancel the mute setting of the volume for the dac output. also handle the adc output data (so) as valid data once the same interval of time has elapsed. 4. immediately after changing the lrclk/bit_clk operation mode, noise may occur in the adc and dac outputs. for this reason, before changing this setting, set the volume for dac output to mute. 5. start supplying the external clock (lrclk, bit_clk) immediately it has been changed prior to changing the lrclk/bit_clk operation mode setting. 6. to prevent popping noises, after changing the lrclk/bit_clk operation mode, following the lapse of an interval of time sufficient for three or more lrclk cycles to be supplied, cancel the mute setting of the volume for the dac output. also handle the adc output data (so) as valid data once the same interval of time has elapsed.
data sheet s15003ej6v0ds 15 pd63335 (c) to pause supply of the external clock (lrclk, bit_clk) while the power is on power down the adc and dac in the sequence described below. to restart the external clock supply, perform steps <2> to <6> of section (a) to start adc, dac operation from the adc, dac power down status (including at power on). <1> set the dac volume register (10h, 11h) and the dac master volume register (14h, 15h) to mute note 1 . <2> power down the adc and dac (use power down control register (18h)). <3> stop the external clock (lrclk, bit_clk) (fix it to high level or low level) note 2 . notes 1. immediately after executing adc, dac power down, noise may occur in the adc and dac outputs. for this reason, before executing power down, set the volume for the dac output to mute. 2. to reliably power down adc and dac, following input of the adc, dac power down command, stop supplying the external clock (lrclk, bit_clk) after supplying lrclk for three cycles or more.
data sheet s15003ej6v0ds 16 pd63335 1.6.3 data format of fsdf2:fsdf1:fsdf0:lrclks = 0:0:0:0 ? clkios = ?0?: input of both bit_clk and lrclk ? clkios = ?1?: output of both bit_clk and lrclk ? bit_clk: 64 f s ? data i/o occurs via the l channel while lrclk is at high level and occurs via the r channel while lrclk is at low level. y si and so have left-justified data input and output. 1.6.4 data format of fsdf2:fsdf1:fsdf0:lrclks = 0:0:0:1 ? clkios = ?0?: input of both bit_clk and lrclk ? clkios = ?1?: output of both bit_clk and lrclk ? bit_clk: 64 f s ? data i/o occurs via the r channel while lrclk is at high level and occurs via the l channel while lrclk is at low level. ? si and so have left-justified data input and output. si l14 l13 l12 l11 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r4 r3 r2 r1 r0 l15 left channel data right channel data so left channel data right channel data lrclk bit_clk 64 fs l14 l13 l12 l11 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r4 r3 r2 r1 r0 l15 si l14 l13 l3 l1 l0 r15 r14 r13 r1 r0 l15 left channel data right channel data so left channel data right channel data lrclk bit_clk 64 fs l15 l13 l2 l1 l0 r15 r2 r1 r0 l2 r2 r3 l14 r14 l3 r13 r3 r4 r4
data sheet s15003ej6v0ds 17 pd63335 1.6.5 data format of fsdf2:fsdf1:fsdf0:lrclks = 0:0:1:0 ? clkios = ?0?: input of both bit_clk and lrclk ? clkios = ?1?: output of both bit_clk and lrclk ? bit_clk: 64 f s ? data i/o occurs via the l channel while lrclk is at high level and occurs via the r channel while lrclk is at low level. ? si has left-justified data input and so has right-justified data output. 1.6.6 data format of fsdf2:fsdf1:fsdf0:lrclks = 0:0:1:1 ? clkios = ?0?: input of both bit_clk and lrclk ? clkios = ?1?: output of both bit_clk and lrclk ? bit_clk: 64 f s ? data i/o occurs via the r channel while lrclk is at high level and occurs via the l channel while lrclk is at low level. ? si has left-justified data input and so has right-justified data output. si l14 l13 l3 l1 l0 r15 r14 r13 r1 r0 l15 left channel data right channel data so left channel data right channel data lrclk bit_clk 64 fs l15 l13 l2 l1 l0 r15 r2 r1 r0 l2 r2 r3 l14 r14 l3 r13 r3 r4 r4 si l14 l13 l3 l1 l0 r15 r14 r13 r1 r0 l15 left channel data right channel data so left channel data right channel data lrclk bit_clk 64 fs l15 l13 l2 l1 l0 r15 r2 r1 r0 l2 r2 r3 l14 r14 l3 r13 r3 r4 r4
data sheet s15003ej6v0ds 18 pd63335 1.6.7 data format of fsdf2:fsdf1:fsdf0:lrclks = 0:1:0:0 ? clkios = ?0?: input of both bit_clk and lrclk ? clkios = ?1?: output of both bit_clk and lrclk ? bit_clk: 64 f s ? data i/o occurs via the l channel while lrclk is at high level and occurs via the r channel while lrclk is at low level. ? si has right-justified data input and so has left-justified data output. 1.6.8 data format of fsdf2:fsdf1:fsdf0:lrclks = 0:1:0:1 ? clkios = ?0?: input of both bit_clk and lrclk ? clkios = ?1?: output of both bit_clk and lrclk ? bit_clk: 64 f s ? data i/o occurs via the r channel while lrclk is at high level and occurs via the l channel while lrclk is at low level. ? si has right-justified data input and so has left-justified data output. si l15 l14 l13 l2 l1 l0 r15 r14 r13 r4 r2 r1 r0 left channel data right channel data so left channel data right channel data lrclk bit_clk 64 fs l15 l14 l13 l3 l2 l1 l0 r15 r14 r13 r4 r2 r1 r0 r3 l3 r3 si l15 l14 l13 l2 l1 l0 r15 r14 r13 r4 r2 r1 r0 left channel data right channel data so left channel data right channel data lrclk bit_clk 64 fs l15 l14 l13 l3 l2 l1 l0 r15 r14 r13 r4 r2 r1 r0 r3 l3 r3
data sheet s15003ej6v0ds 19 pd63335 1.6.9 data format of fsdf2:fsdf1:fsdf0:lrclks = 0:1:1:0 ? clkios = ?0?: input of both bit_clk and lrclk ? clkios = ?1?: output of both bit_clk and lrclk ? bit_clk: 64 f s ? data i/o occurs via the l channel while lrclk is at high level and occurs via the r channel while lrclk is at low level. ? si and so have right-justified data input and output. 1.6.10 data format of fsdf2:fsdf1:fsdf0:lrclks = 0:1:1:1 ? clkios = ?0?: input of both bit_clk and lrclk ? clkios = ?1?: output of both bit_clk and lrclk ? bit_clk: 64 f s ? data i/o occurs via the r channel while lrclk is at high level and occurs via the l channel while lrclk is at low level. ? si and so have right-justified data input and output. si l15 l14 l13 l2 l1 l0 r15 r14 r13 r4 r2 r1 r0 left channel data right channel data so left channel data right channel data lrclk bit_clk 64 fs l3 r3 l15 l14 l13 l2 l1 l0 r15 r14 r13 r4 r2 r1 r0 l3 r3 si l15 l14 l13 l2 l1 l0 r15 r14 r13 r4 r2 r1 r0 left channel data right channel data so left channel data right channel data lrclk bit_clk 64 fs l3 r3 l15 l14 l13 l2 l1 l0 r15 r14 r13 r4 r2 r1 r0 l3 r3
data sheet s15003ej6v0ds 20 pd63335 1.6.11 data format of fsdf2:fsdf1:fsdf0:lrclks = 1:0:0:0 ? clkios = ?0?: input of both bit_clk and lrclk ? clkios = ?1?: output of both bit_clk note and lrclk ? bit_clk: 48 f s ? data i/o occurs via the l channel while lrclk is at high level and occurs via the r channel while lrclk is at low level. ? si and so have left-justified data input and output. note the duty factor of output bit_clk is not 50%. 1.6.12 data format of fsdf2:fsdf1:fsdf0:lrclks = 1:0:0:1 ? clkios = ?0?: input of both bit_clk and lrclk ? clkios = ?1?: output of both bit_clk note and lrclk ? bit_clk: 48 f s ? data i/o occurs via the r channel while lrclk is at high level and occurs via the l channel while lrclk is at low level. ? si and so have left-justified data input and output. note the duty factor of output bit_clk is not 50%. si l14 l13 l12 l11 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r4 r3 r2 r1 r0 l15 left channel data right channel data so left channel data right channel data lrclk bit_clk 48 fs l14 l13 l12 l11 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r4 r3 r2 r1 r0 l15 si l14 l13 l12 l11 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r4 r3 r2 r1 r0 l15 left channel data right channel data so left channel data right channel data lrclk bit_clk 48 fs l14 l13 l12 l11 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r4 r3 r2 r1 r0 l15
data sheet s15003ej6v0ds 21 pd63335 1.6.13 data format of fsdf2:fsdf1:fsdf0:lrclks = 1:0:1:0 ? clkios = ?0?: input of both bit_clk and lrclk ? clkios = ?1?: output of both bit_clk note and lrclk ? bit_clk: 48 f s ? data i/o occurs via the l channel while lrclk is at high level and occurs via the r channel while lrclk is at low level. ? si has left-justified data input and so has right-justified data output. note the duty factor of output bit_clk is not 50%. 1.6.14 data format of fsdf2:fsdf1:fsdf0:lrclks = 1:0:1:1 ? clkios = ?0?: input of both bit_clk and lrclk ? clkios = ?1?: output of both bit_clk note and lrclk ? bit_clk: 48 f s ? data i/o occurs via the r channel while lrclk is at high level and occurs via the l channel while lrclk is at low level. ? si has left-justified data input and so has right-justified data output. note the duty factor of output bit_clk is not 50%. si l14 l13 l8 l6 l5 l4 l3 l1 r15 r14 r13 r5 r4 r3 r1 r0 l15 left channel data right channel data so left channel data right channel data lrclk bit_clk 48 fs l14 l13 l12 l11 l9 l8 l2 l1 l0 r15 r14 r13 r12 r11 r9 r8 r2 r1 r0 l15 l2 r2 l7 r6 r7 l10 r10 si l14 l13 l8 l6 l5 l4 l3 l1 r15 r14 r13 r5 r4 r3 r1 r0 l15 left channel data right channel data so left channel data right channel data lrclk bit_clk 48 fs l14 l13 l12 l11 l9 l8 l2 l1 l0 r15 r14 r13 r12 r11 r9 r8 r2 r1 r0 l15 l2 r2 l7 r6 r7 l10 r10
data sheet s15003ej6v0ds 22 pd63335 1.6.15 data format of fsdf2:fsdf1:fsdf0:lrclks = 1:1:0:0 ? clkios = ?0?: input of both bit_clk and lrclk ? clkios = ?1?: output of both bit_clk note and lrclk ? bit_clk: 48 f s ? data i/o occurs via the l channel while lrclk is at high level and occurs via the r channel while lrclk is at low level. ? si has right-justified data input and so has left-justified data output. note the duty factor of output bit_clk is not 50%. 1.6.16 data format of fsdf2:fsdf1:fsdf0:lrclks = 1:1:0:1 ? clkios = ?0?: input of both bit_clk and lrclk ? clkios = ?1?: output of both bit_clk note and lrclk ? bit_clk: 48 f s ? data i/o occurs via the r channel while lrclk is at high level and occurs via the l channel while lrclk is at low level. ? si has right-justified data input and so has left-justified data output. note the duty factor of output bit_clk is not 50%. si l15 l14 l13 l12 l11 l10 l9 l8 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r2 r1 r0 left channel data right channel data so left channel data right channel data lrclk bit_clk 48 fs l15 l14 l13 l8 l7 l6 l5 l3 l2 l1 r15 r14 r13 r7 r6 r5 r4 r2 r1 r0 l4 r3 si l15 l14 l13 l12 l11 l10 l9 l8 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r2 r1 r0 left channel data right channel data so left channel data right channel data lrclk bit_clk 48 fs l15 l14 l13 l8 l7 l6 l5 l3 l2 l1 r15 r14 r13 r7 r6 r5 r4 r2 r1 r0 l4 r3
data sheet s15003ej6v0ds 23 pd63335 1.6.17 data format of fsdf2:fsdf1:fsdf0:lrclks = 1:1:1:0 (initial value) ? clkios = ?0?: input of both bit_clk and lrclk ? clkios = ?1?: output of both bit_clk and lrclk ? bit_clk: 32 f s ? data i/o occurs via the l channel while lrclk is at high level and occurs via the r channel while lrclk is at low level. 1.6.18 data format of fsdf2:fsdf1:fsdf0:lrclks = 1:1:1:1 ? clkios = ?0?: input of both bit_clk and lrclk ? clkios = ?1?: output of both bit_clk and lrclk ? bit_clk: 32 f s ? data i/o occurs via the r channel while lrclk is at high level and occurs via the l channel while lrclk is at low level. 1.7 usage precautions analog input pins may influence the internal circuit characteristics if register mute is cancelled while they are open. therefore, ground all unused analog input pins via a capacitor (refer to figure 1-5 ) and set related registers to mute. figure 1-5. example of handling of unused analog input pin si l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 left channel data right channel data so l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 left channel data right channel data lrclk bit_clk 32 fs si l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 left channel data right channel data so l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 left channel data right channel data lrclk bit_clk 32 fs pd63335 0.1 f
data sheet s15003ej6v0ds 24 pd63335 2. registers a register map of the pd63335 is shown below. table 2-1. pd63335 register map address [a7:a0] read write name d7 d6 d5 d4 d3 d2 d1 d0 default 80h 00h reset and clock status select 0 sick 0 rrst rate1 rate0 lrclks clkios 40h 81h 01h interface timing 0 sick 0 0 0 fsdf2 fsdf1 fsdf0 47h 82h 02h ads select 0 sick adsl2 adsl1 adsl0 adsr2 adsr1 adsr0 40h 83h 03h adcl gain 0 sick 0 adlm adlv3 adlv2 adlv1 adrv0 50h 84h 04h adcr gain 0 sick 0 adrm adrv3 adrv2 adrv1 adrv0 50h 85h 05h in1l volume 0 sick in1lm in1lv4 in1lv3 in1lv2 in1lv1 in1lv0 68h 86h 06h in1r volume 0 sick in1rm in1rv4 in1rv3 in1rv2 in1rv1 in1rv0 68h 87h 07h in2l volume 0 sick in2lm in2lv4 in2lv3 in2lv2 in2lv1 in2lv0 68h 88h 08h in2r volume 0 sick in2rm in2rv4 in2rv3 in2rv2 in2rv1 in2rv0 68h 89h 09h in3l volume 0 sick in3lm in3lv4 in3lv3 in3lv2 in3lv1 in3lv0 68h 8ah 0ah in3r volume 0 sick in3rm in3rv4 in3rv3 in3rv2 in3rv1 in3rv0 68h 8bh 0bh in4l volume 0 sick in4lm in4lv4 in4lv3 in4lv2 in4lv1 in4lv0 68h 8ch 0ch in4r volume 0 sick in4rm in4rv4 in4rv3 in4rv2 in4rv1 in4rv0 68h 8dh 0dh in5 volume 0 sick in5m in5v4 in5v3 in5v2 in5v1 in5v0 68h 8eh 0eh mic volume 0 sick micm micv4 micv3 micv2 micv1 micv0 68h 8fh 0fh in6 volume 0 sick in6m in6v3 in6v2 in6v1 in6v0 0 60h 90h 10h dacl volume 0 sick dalm dalv4 dalv3 dalv2 dalv1 dalv0 68h 91h 11h dacr volume 0 sick darm darv4 darv3 darv2 darv1 darv0 68h 92h 12h outl master volume 0 sick omlm omlv4 omlv3 omlv2 omlv1 omlv0 60h 93h 13h outr master volume 0 sick omrm omrv4 omrv3 omrv2 omrv1 omrv0 60h 94h 14h dalr master volume 0 sick dmlm dmlv4 dmlv3 dmlv2 dmlv1 dmlv0 60h 95h 15h dacr master volume 0 sick dmrm dmrv4 dmrv3 dmrv2 dmrv1 dmrv0 60h 96h 16h mono volume 0 sick mnmm mnmv4 mnmv3 mnmv2 mnmv1 mnmv0 60h 97h 17h path select 0 sick 0 1 mix ms mc20 lpbk 50h 98h 18h power down control/status 0sick0digpd vrefpd mixpd dacpd adcpd 43h ? 7fh warm reset rw7 rw6 rw5 rw4 rw3 rw2 rw1 rw0 00h
data sheet s15003ej6v0ds 25 pd63335 cautions 1. read/write access is prohibited for all registers that are not included in this table (i.e., for all non-existent registers). 2. read access is prohibited for the warm reset register (7fh). 3. a7, the msb of the address, indicates the command read/write attribute. 4. the write data to write address 00h and 10h becomes valid after lrclk is input (or output) for one clock cycle or more. 2.1 individual registers 2.1.1 serial command interface check bit (sick) the d7 and d6 bits of all registers except the warm reset register (7fh) can be used to check the serial command interface transfer results. when write is performed to the pd63335 register, ?1? is always written to the sick bit. when the initial state and serial command interface operate normally, ?1? is always written to the sick bit and the d7 and d6 bits of all the registers except the warm reset register (7fh) remain ?01?. if for some reason the d7 and d6 bits become other than ?01? during write, ?0? is written to sick. in other words, when the d7 and d6 bits among the register values read from the host processor are ?00?, bit displacement occurs during serial command interface write or read, and register access may not be performed normally. if the sick bit of the read register is ?0?, perform a warm reset and execute a digital command interface reset. table 2-2 shows the relationship between the values written to the d7 and d6 bits and the sick bit. table 2-2. sick bit setting values write [d7:d6] sick setting value read [d7:d6] command i/f status 00 0 00 abnormal 01 1 01 normal 10 0 00 abnormal 11 0 00 abnormal 2.1.2 reset/clock status register (00h) read address write address d7 d6 d5 d4 d3 d2 d1 d0 default 80h 00h 0 sick 0 rrst rate1 rate0 lrclks clkios 40h this register is used to make register reset settings, serial data interface settings, and sampling rate settings. the bits and settings are described as follows. when 5xh is written to this register, a register reset is executed (refer to 1.4 reset for details of the register reset.). a register reset sets default values in all registers except the reset/clock status register (00h), interface/timing register (01h), and power down control register (18h). this register?s default value is 40h (register reset: off, sampling rate setting: f mclk /3072, lrclk setting: when lrclk = high level, l channel pcm data i/o, bit_clk/lrclk: input).
data sheet s15003ej6v0ds 26 pd63335 table 2-3. bits and settings in reset/clock status register (00h) bit name value description remark d4 rrst 1 register reset ? 00 f s = f mclk /3072 (8 khz @ f mclk = 24.576 mhz) default 01 f s = f mclk /1536 (16 khz @ f mclk = 24.576 mhz) ? 10 f s = f mclk /768 (32 khz @ f mclk = 24.576 mhz) ? d3, d2 rate [1:0] 11 f s = f mclk /512 (48 khz @ f mclk = 24.576 mhz) ? 0 when lrclk is at high level, l channel data default d1 lrclks 1 when lrclk is at high level, r channel data ? 0 lrclk and bit_clk are both input default d0 clkios 1 lrclk and bit_clk are both output ? remark f s : sampling rate f mclk : master clock (input frequency from xtl_in pin) 2.1.3 interface/timing register (01h) read address write address d7 d6 d5 d4 d3 d2 d1 d0 default 81h 01h 0 sick 0 0 0 fsdf2 fsdf1 fsdf0 47h this register is used to set the data i/o method for the serial data interface. the default value is 47h. table 2-4. format of interface/timing register (01h) audio data format (2?s complement, msb first) bit name value bit clocks per frame pcm i nput data si pcm output data so 000 64 left justified left justified 001 64 left justified right justified 010 64 right justified left justified 011 64 right justified right justified 100 48 left justified left justified 101 48 left justified right justified 110 48 right justified left justified d2 to d0 fsdf [2:0] 111 32 (default) ??
data sheet s15003ej6v0ds 27 pd63335 2.1.4 input select register (02h) read address write address d7 d6 d5 d4 d3 d2 d1 d0 default 82h 02h 0 sick adsl2 adsl1 adsl0 adsr2 adsr1 adsr0 40h this register is used to make adc input settings. the multiplexer that comes before the adc can be set independently to l channel or r channel. the default value is 40h (mic input). table 2-5. settings in input select register (02h) l channel r channel adsl [2:0] l channel adc input selection adsr [2:0] r channel adc input selection 000 mic (default value) 000 mic (default value) 001 in1l 001 in1r 010 in2l 010 in2r 011 in3l 011 in3r 100 in4l 100 in4r 101 stereo mix/l 101 stereo mix/r 110 mono mix 110 mono mix 111 in5 111 in5 remarks 1. stereo mix: output of output-side mixer is used as output of input-side multiplexer (adc input). 2. mono mix: dac mono output is used as output of input-side multiplexer (adc input).
data sheet s15003ej6v0ds 28 pd63335 2.1.5 adc input gain registers (03h, 04h) read address write address d7 d6 d5 d4 d3 d2 d1 d0 default 83h 03h 0 sick 0 adlm adlv3 adlv2 adlv1 adlv0 50h 84h 04h 0 sick 0 adrm adrv3 adrv2 adrv1 adrv0 50h these registers are used to set the gain for the output signal from the multiplexer that is input to the adc. the correspondence between bits and gain settings is shown below. gain can be set in a range from 0.0 db to +22.5 db, in 1.5 db steps. the default value is 50h (gain: 0 db, mute: on). ? adlm: l channel adc input mute control bit ? adrm: r channel adc input mute control bit ? adlv[3:0]: l channel adc input gain control bits ? adrv[3:0]: r channel adc input gain control bits table 2-6. correspondence of bits and gain settings in adc input gain registers (03h, 04h) adlm/adrm adlv[3:0]/adrv[3:0] gain 0 0000 0 db 0 0001 +1.5 db ?? ? ?? ? ?? ? 0 1110 +21.0 db 0 1111 +22.5 db 1 xxxx mute 1 0000 default
data sheet s15003ej6v0ds 29 pd63335 2.1.6 in1 volume registers (05h, 06h) read address write address d7 d6 d5 d4 d3 d2 d1 d0 default 85h 05h 0 sick in1lm in1lv4 in1lv3 in1lv2 in1lv1 in1lv0 68h 86h 06h 0 sick in1rm in1rv4 in1rv3 in1rv2 in1rv1 in1rv0 68h these registers are used to set the in1 input signal?s mixer input volume. the correspondence between bits and gain settings is shown below. gain can be set in a range from +12.0 db to ?34.5 db, in 1.5 db steps. the default value is 68h (gain: 0 db, mute: on). ? in1lm: in1 l channel mixer input mute control bit ? in1rm: in1 r channel mixer input mute control bit ? in1lv[4:0]: in1 l channel mixer input gain control bits ? in1rv[4:0]: in1 r channel mixer input gain control bits table 2-7. correspondence of bits and gain settings in in1 volume registers (05h, 06h) in1lm/in1rm in1lv[4:0]/in1rv[4:0] gain 0 0 0000 +12.0 db 0 0 0001 +10.5 db ?? ? ?? ? ?? ? 0 0 1000 0 db ?? ? ?? ? ?? ? 0 1 1110 ? 33.0 db 0 1 1111 ? 34.5 db 1 x xxxx mute 1 0 1000 default
data sheet s15003ej6v0ds 30 pd63335 2.1.7 in2 volume registers (07h, 08h) read address write address d7 d6 d5 d4 d3 d2 d1 d0 default 87h 07h 0 sick in2lm in2lv4 in2lv3 in2lv2 in2lv1 in2lv0 68h 88h 08h 0 sick in2rm in2rv4 in2rv3 in2rv2 in2rv1 in2rv0 68h these registers are used to set the in2 input signal?s mixer input volume. the correspondence between bits and gain settings is shown below. gain can be set in a range from +12.0 db to ?34.5 db, in 1.5 db steps. the default value is 68h (gain: 0 db, mute: on). ? in2lm: in2 l channel mixer input mute control bit ? in2rm: in2 r channel mixer input mute control bit ? in2lv[4:0]: in2 l channel mixer input gain control bits ? in2rv[4:0]: in2 r channel mixer input gain control bits table 2-8. correspondence of bits and gain settings in in2 volume registers (07h, 08h) in2lm/in2rm in2lv[4:0]/in2rv[4:0] gain 0 0 0000 +12.0 db 0 0 0001 +10.5 db ?? ? ?? ? ?? ? 0 0 1000 0 db ?? ? ?? ? ?? ? 0 1 1110 ? 33.0 db 0 1 1111 ? 34.5 db 1 x xxxx mute 1 0 1000 default
data sheet s15003ej6v0ds 31 pd63335 2.1.8 in3 volume registers (09h, 0ah) read address write address d7 d6 d5 d4 d3 d2 d1 d0 default 89h 09h 0 sick in3lm in3lv4 in3lv3 in3lv2 in3lv1 in3lv0 68h 8ah 0ah 0 sick in3rm in3rv4 in3rv3 in3rv2 in3rv1 in3rv0 68h these registers are used to set the in3 input signal?s mixer input volume. the correspondence between bits and gain settings is shown below. gain can be set in a range from +12.0 db to ?34.5 db, in 1.5 db steps. the default value is 68h (gain: 0 db, mute: on). ? in3lm: in3 l channel mixer input mute control bit ? in3rm: in3 r channel mixer input mute control bit ? in3lv[4:0]: in3 l channel mixer input gain control bits ? in3rv[4:0]: in3 r channel mixer input gain control bits table 2-9. correspondence of bits and gain settings in in3 volume registers (09h, 0ah) in3lm/in3rm in3lv[4:0]/in3rv[4:0] gain 0 0 0000 +12.0 db 0 0 0001 +10.5 db ?? ? ?? ? ?? ? 0 0 1000 0 db ?? ? ?? ? ?? ? 0 1 1110 ? 33.0 db 0 1 1111 ? 34.5 db 1 x xxxx mute 1 0 1000 default
data sheet s15003ej6v0ds 32 pd63335 2.1.9 in4 volume registers (0bh, 0ch) read address write address d7 d6 d5 d4 d3 d2 d1 d0 default 8bh 0bh 0 sick in4lm in4lv4 in4lv3 in4lv2 in4lv1 in4lv0 68h 8ch 0ch 0 sick in4rm in4rv4 in4rv3 in4rv2 in4rv1 in4rv0 68h these registers are used to set the in4 input signal?s mixer input volume. the correspondence between bits and gain settings is shown below. gain can be set in a range from +12.0 db to ?34.5 db, in 1.5 db steps. the default value is 68h (gain: 0 db, mute: on). ? in4lm: in4 l channel mixer input mute control bit ? in4rm: in4 r channel mixer input mute control bit ? in4lv[4:0]: in4 l channel mixer input gain control bits ? in4rv[4:0]: in4 r channel mixer input gain control bits table 2-10. correspondence of bits and gain settings in in4 volume registers (0bh, 0ch) in4lm/in4rm in4lv[4:0]/in4rv[4:0] gain 0 0 0000 +12.0 db 0 0 0001 +10.5 db ?? ? ?? ? ?? ? 0 0 1000 0 db ?? ? ?? ? ?? ? 0 1 1110 ? 33.0 db 0 1 1111 ? 34.5 db 1 x xxxx mute 1 0 1000 default
data sheet s15003ej6v0ds 33 pd63335 2.1.10 in5 volume register (0dh) read address write address d7 d6 d5 d4 d3 d2 d1 d0 default 8dh 0dh 0 sick in5m in5v4 in5v3 in5v2 in5v1 in5v0 68h this register is used to set the in5 input signal?s mixer input volume. the correspondence between bits and gain settings is shown below. gain can be set in a range from +12.0 db to ?34.5 db, in 1.5 db steps. the default value is 68h (gain: 0 db, mute: on). ? in5m: in5 mixer input mute control bit ? in5v[4:0]: in5 mixer input gain control bits table 2-11. correspondence of bits and gain settings in in5 volume register (0dh) in5m in5v[4:0] gain 0 0 0000 +12.0 db 0 0 0001 +10.5 db ?? ? ?? ? ?? ? 0 0 1000 0 db ?? ? ?? ? ?? ? 0 1 1110 ? 33.0 db 0 1 1111 ? 34.5 db 1 x xxxx mute 1 0 1000 default
data sheet s15003ej6v0ds 34 pd63335 2.1.11 mic volume register (0eh) read address write address d7 d6 d5 d4 d3 d2 d1 d0 default 8eh 0eh 0 sick micm micv4 micv3 micv2 micv1 micv0 68h this register is used to set the mic?s mixer input volume. the correspondence between bits and gain settings is shown below. gain can be set in a range from +12.0 db to ?34.5 db, in 1.5 db steps. the default value is 68h (gain: 0 db, mute: on). ? micm: mic mixer input mute control bit ? micv[4:0]: mic mixer input gain control bits table 2-12. correspondence of bits and gain settings in mic volume register (0eh) micm micv[4:0] gain 0 0 0000 +12.0 db 0 0 0001 +10.5 db ?? ? ?? ? ?? ? 0 0 1000 0 db ?? ? ?? ? ?? ? 0 1 1110 ? 33.0 db 0 1 1111 ? 34.5 db 1 x xxxx mute 1 0 1000 default
data sheet s15003ej6v0ds 35 pd63335 2.1.12 in6 volume register (0fh) read address write address d7 d6 d5 d4 d3 d2 d1 d0 default 8fh 0fh 0 sick in6m in6v3 in6v2 in6v1 in6v0 0 60h this register is used to set the in6 input signal?s mixer input volume. the correspondence between bits and gain settings is shown below. gain can be set in a range from 0 db to ?45 db, in 3.0 db steps. the default value is 60h (gain: 0 db, mute: on). ? in6m: in6 mixer input mute control bit ? in6v[3:0]: in6 mixer input gain control bits table 2-13. correspondence of bits and gain settings in in6 volume register (0fh) in6m in6v[3:0] gain 0 0000 0 db 0 0001 ? 3.0 db ?? ? ?? ? ?? ? 0 1110 ? 42.0 db 0 1111 ? 45.0 db 1 xxxx mute 1 0000 default
data sheet s15003ej6v0ds 36 pd63335 2.1.13 dac volume registers (10h, 11h) read address write address d7 d6 d5 d4 d3 d2 d1 d0 default 90h 10h 0 sick dalm dalv4 dalv3 dalv2 dalv1 dalv0 68h 91h 11h 0 sick darm darv4 darv3 darv2 darv1 darv0 68h these registers are used to set the dac output signal?s mixer input volume. the correspondence between bits and gain settings is shown below. gain can be set in a range from +12.0 db to ?34.5 db, in 1.5 db steps. the default value is 68h (gain: 0 db, mute: on). ? dalm: dac l channel mixer input mute control bit ? darm: dac r channel mixer input mute control bit ? dalv[4:0]: dac l channel mixer input gain control bits ? darv[4:0]: dac r channel mixer input gain control bits table 2-14. correspondence of bits and gain settings in dac volume registers (10h, 11h) dalm/darm dalv[4:0]/darv[4:0] gain 0 0 0000 +12.0 db 0 0 0001 +10.5 db ?? ? ?? ? ?? ? 0 0 1000 0 db ?? ? ?? ? ?? ? 0 1 1110 ? 33.0 db 0 1 1111 ? 34.5 db 1 x xxxx mute 1 0 1000 default
data sheet s15003ej6v0ds 37 pd63335 2.1.14 out master volume registers (12h, 13h) read address write address d7 d6 d5 d4 d3 d2 d1 d0 default 92h 12h 0 sick omlm omlv4 omlv3 omlv2 omlv1 omlv0 60h 93h 13h 0 sick omrm omrv4 omrv3 omrv2 omrv1 omrv0 60h these registers are used to set the master volume for outl and outr and the gain for mixer output to the outl and outr pins. the correspondence between bits and gain settings is shown below. gain can be set in a range from 0 db to ?46.5 db, in 1.5 db steps. the default value is 60h (gain: 0 db, mute: on). ? omlm: outl output mute control bit ? omrm: outr output mute control bit ? omlv[4:0]: outl output gain control bits ? omrv[4:0]: outr output gain control bits table 2-15. correspondence of bits and gain settings in out master volume registers (12h, 13h) omlm/omrm omlv[4:0]/omrv[4:0] gain 0 0 0000 0 db 0 0 0001 ? 1.5 db ?? ? ?? ? ?? ? 0 1 1110 ? 45.0 db 0 1 1111 ? 46.5 db 1 x xxxx mute 1 0 0000 default
data sheet s15003ej6v0ds 38 pd63335 2.1.15 dac master volume registers (14h, 15h) read address write address d7 d6 d5 d4 d3 d2 d1 d0 default 94h 14h 0 sick dmlm dmlv4 dmlv3 dmlv2 dmlv1 dmlv0 60h 95h 15h 0 sick dmrm dmrv4 dmrv3 dmrv2 dmrv1 dmrv0 60h these registers are used to set the master volume for dacl and dacr. the correspondence between bits and gain settings is shown below. gain can be set in a range from 0 db to ?46.5 db, in 1.5 db steps. the default value is 60h (gain: 0 db, mute: on). ? dmlm: dacl output mute control bit ? dmrm: dacr output mute control bit ? dmlv[4:0]: dacl output gain control bits ? dmrv[4:0]: dacr output gain control bits table 2-16. correspondence of bits and gain settings in dac master volume registers (14h, 15h) dmlm/dmrm dmlv[4:0]/dmrv[4:0] gain 0 0 0000 0 db 0 0 0001 ? 1.5 db ?? ? ?? ? ?? ? 0 1 1110 ? 45.0 db 0 1 1111 ? 46.5 db 1 x xxxx mute 1 0 0000 default
data sheet s15003ej6v0ds 39 pd63335 2.1.16 mono output master volume register (16h) read address write address d7 d6 d5 d4 d3 d2 d1 d0 default 96h 16h 0 sick mnmm mnmv4 mnmv3 mnmv2 mnmv1 mnmv0 60h this register is used to set the master volume for mono output. the correspondence between bits and gain settings is shown below. gain can be set in a range from 0 db to ?46.5 db, in 1.5 db steps. the default value is 60h (gain: 0 db, mute: on). ? mnmm: mono output mute control bit ? mnmv[4:0]: mono output gain control bits table 2-17. correspondence of bits and gain settings in mono output master volume register (16h) mnmm mnmv[4:0] gain 0 0 0000 0 db 0 0 0001 ? 1.5 db ?? ? ?? ? ?? ? 0 1 1110 ? 45.0 db 0 1 1111 ? 46.5 db 1 x xxxx mute 1 0 0000 default
data sheet s15003ej6v0ds 40 pd63335 2.1.17 path select register (17h) read address write address d7 d6 d5 d4 d3 d2 d1 d0 default 97h 17h 0 sick 0 1 mix ms mc20 lpbk 50h this register is used to set internal signal switching. the default value is 50h. table 2-18. signal switching settings in path select register (17h) bit mnmv[4:0] setting 0mixer mix mono out select 1mic 0mic1 ms mic select 1mic2 0 +0 db mc20 mic gain select 1 +20 db 0off lpbk adc/dac analog loop-back (test mode) 1on ? mix: this selects input of mono output master volume, using either monaural signals from the mixer or monaural signals from the mic. ? ms: this selects either mic1 or mic2 as the source for input to the mic amp. ? mc20: this sets the mic amp?s gain as either 0 db or 20 db. ? lpbk: this selects analog loop-back mode. when in analog loop-back mode, the output from adc is internally input directly to the dac, which enables the analog circuit?s operations and volume settings to be verified.
data sheet s15003ej6v0ds 41 pd63335 2.1.18 power down control register (18h) read address write address d7 d6 d5 d4 d3 d2 d1 d0 default 98h 18h 0 sick 0 digpd vrefpd mixpd dacpd adcpd 43h this register is used to set the power down mode. when one of its bits is set to ?1?, the specified block is set to power down mode. the relation between bits and internal circuits set to power down mode are shown in figure 2-1 power down mode block diagram . the default value is 40h. table 2-19. bits in power down control register (18h) and power down functions bit function digpd digital block/clock power down vrefpd analog block power down mixpd mixer power down (valid when analog block is on) dacpd dac power down adcpd adc power down table 2-20. bits in power down control register (18h) and internal circuits set to power down mode bit adc dac mixer volume master volume vref interface internal clock digpd pd pd x x x pd pd vrefpd pd pd pd pd pd x x mixpd x x pd pd x x x dacpdxpdxxxxx adcpdpdxxxxxx cautions 1. when the bit_clk and lrclk i/o settings are set to input, input of the bit_clk and lrclk signals is required before releasing power down mode. 2. digpd (digital block/clock power down) is released by a cold or warm reset. if a warm reset is executed, the internal registers can be accessed, but because the digpd bit remains set to 1, some of the digital circuit operations will not resume. to ensure the resumption of these operations, therefore, set the digpd bit to 0 after a warm reset. remark x: normal operation, pd: power down mode
data sheet s15003ej6v0ds 42 pd63335 figure 2-1. power down mode block diagram digpd dacpd vrefpd mixpd adcpd ? 6 db mixer mc20 0 db/ 20 db multiplexer multiplexer mix mixer mixer mixer mixer ms so si lrclk mswdt msrdt msclk reset xtl_in xtl_out bit_clk mic2 mic1 in2l in1l in4l in5 in3l stereo mix/l mono mix stereo mix/r in1r in6 mono_out in3r in4r outl dacl dacr outr in2r digital data interface digital command interface analog output pins analog input pins in4r in3r in2r in1r mic mono mix in5 in1r in2r in3r in4r stereo mix/r in5 in6 mic mic in4l in3l in2l in1l in5 mono mix in1l in2l mic stereo mix/l in3l in4l ? 6 db mixer digital filter i/o interface interpolator interpolator dac dac decimator decimator adc adc loop-back (test mode) dac mono
data sheet s15003ej6v0ds 43 pd63335 2.1.19 warm reset register (7fh) address d7 d6 d5 d4 d3 d2 d1 d0 default 7fh rw7 rw6 rw5 rw4 rw3 rw2 rw1 rw0 00h when ffh is written to this register, the digital interface is initialized. read access to this register and writing to other than ffh are prohibited. table 2-21. settings for warm reset register (7fh) rw [7:0] function 1111 1111 warm reset execution
data sheet s15003ej6v0ds 44 pd63335 3. electrical specifications absolute maximum ratings parameter symbol conditions ratings unit digital block power supply voltage dv dd ? 0.3 to +4.6 v analog block power supply voltage av dd ? 0.3 to +4.6 v input current i i pins except power supply and ground ? 10 to +10 ma digital input voltage dv i all digital input pins ? 0.3 to dv dd + 0.3 v analog input voltage av i all analog input pins ? 0.3 to av dd + 0.3 v operating ambient temperature t a device ambient temperature ? 40 to +85 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operation range (dv ss = av ss = 0 v, load capacitance = 20 pf) parameter symbol conditions min. typ. max. unit digital block power supply voltage dv dd 3.0 3.3 3.6 v analog block power supply voltage av dd 3.0 3.3 3.6 v operating ambient temperature t a device ambient temperature ? 40 +25 +85 c master clock frequency f mclk 1.024 ? 24.576 mhz master clock duty factor note f dty 45 50 55 % sampling frequency f s 0.4 ? 48 khz digital input voltage (high level) v ih 1.95 ?? v digital input voltage (low level) v il ?? 1.26 v analog input signal voltage v i ? 0.7 ? v r.m.s. analog output pin load resistance r l analog output pin 10 ?? k ? note using a master clock duty factor that is outside the recommended operation range may result in degradation of analog characteristics.
data sheet s15003ej6v0ds 45 pd63335 digital block dc characteristics (dv dd = av dd = 3.3 v, dv ss = av ss = 0 v, t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit digital block current consumption i dv1 during normal operation ? 10.0 15.0 ma digital standby current i dv2 during power down mode ? 0.0 0.1 ma input leakage current i li ? 10.0 ? +10.0 a output leakage current i lo during high impedance mode ? 10.0 ? +10.0 a input voltage, high v ih 1.95 ?? v input voltage, low v il ?? 1.26 v output voltage, high v oh output current = ?5.0 ma 2.70 ?? v output voltage, low v ol output current = 5.0 ma ?? 0.36 v pull-up resistance r up 20 50 100 k ? analog block dc characteristics (dv dd = av dd = 3.3 v, dv ss = av ss = 0 v, t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit analog block current consumption i av1 during normal operation ? 40.0 50.0 ma analog standby current i av2 during power down mode ? 0.0 0.1 ma reference voltage v ref 1.35 1.4 1.45 v v ai except for mic input ? 0.7 ? v r.m.s. v mi0 +20 db = on ? 0.07 ? v r.m.s. analog input voltage v mi20 +20 db = off ? 0.7 ? v r.m.s. analog output voltage v ao ? 0.7 ? v r.m.s. input impedance a lb 10 ?? k ?
data sheet s15003ej6v0ds 46 pd63335 ad block transmission characteristics (unless otherwise specified, dv dd = av dd = 3.3 v, dv ss = av ss = 0 v, t a = ?40 to +85 c, sampling frequency = 48 khz, bandwidth = 20 hz to 19.2 khz, input signal = 1 khz) parameter symbol conditions min. typ. max. unit ad dynamic range dr x ? 60 db input 75 85 ? db ad total harmonic distortion thd x ? 3 db input ? 0.01 0.02 % ad absolute gain g x 0 db input ? 1.0 0.5 +1.0 db ad frequency gain characteristic gr x 20 hz to 19.2 khz ? 0.25 0.1 +0.25 db ad offset voltage v offx ? 50 10 +50 mv ad crosstalk xtk x vs. input channel ?? 85 ? 70 db ad full-scale analog input amplitude note vifs x ? 0.7 ? v r.m.s. note the ad full-scale analog input amplitude (vifs x ) indicates the input amplitude of the internal ad converter. before inputting to the ad converter, calculate the amplitude that does not exceed this value from the setting values of mic amp and each volume. da block transmission characteristics (unless otherwise specified, dv dd = av dd = 3.3 v, dv ss = av ss = 0 v, t a = ?40 to +85 c, sampling frequency = 48 khz, bandwidth = 20 hz to 19.2 khz, input signal = 1 khz) parameter symbol conditions min. typ. max. unit da dynamic range dr r ? 60 db input 80 90 ? db da total harmonic distortion thd r ? 3 db input ? 0.01 0.02 % da absolute gain g r 0 db input ? 1.0 0.5 +1.0 db da frequency gain characteristic gr r 20 hz to 19.2 khz ? 0.25 0.1 +0.25 db da offset voltage v offr ? 50 10 +50 mv da crosstalk xtk r vs. input channel ?? 85 ? 70 db da full-scale analog output amplitude vofs r ? 0.7 ? v r.m.s. mic block transmission characteristics (unless otherwise specified, dv dd = av dd = 3.3 v, dv ss = av ss = 0 v, t a = ?40 to +85 c, sampling frequency = 48 khz, bandwidth = 20 hz to 19.2 khz, input signal = 1 khz) parameter symbol conditions min. typ. max. unit mic absolute gain g mc20 ? 20 db input, +20 db = on 18 20 22 db
data sheet s15003ej6v0ds 47 pd63335 mixer block transmission characteristics (unless otherwise specified, dv dd = av dd = 3.3 v, dv ss = av ss = 0 v, t a = ?40 to +85 c, sampling frequency = 48 khz, bandwidth = 20 hz to 19.2 khz, input signal = 1 khz) parameter symbol conditions min. typ. max. unit dynamic range dr a ? 60 db input 85 90 ? db total harmonic distortion thd a ? 3 db input ? 0.01 0.02 % absolute gain g a 0 db input ? 1.0 0.5 +1.0 db frequency gain characteristic gr a 20 hz to 19.2 khz ? 0.25 0.1 +0.25 db offset voltage v offa ? 50 10 +50 mv crosstalk xtk a vs. input channel ?? 80 ? 70 db full-scale analog input amplitude vifs a ? 0.7 ? v r.m.s. full-scale analog output amplitude vofs a ? 0.7 ? v r.m.s. ac characteristics, digital block (unless otherwise specified, dv dd = av dd = 3.3 v, dv ss = av ss = 0 v, t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit _______ reset rise time t rrst time for v dd to change from 10% to 90% ?? 1.0 s _______ reset low-level width notes 1, 2 t rstl 4.0 ?? s master clock frequency note 3 f mclk 1.024 ? 24.576 mhz notes 1. t rstl is the time required for initialization of this lsi. when performing a reset, set _______ reset to active (low level) for t rstl period. 2. the internal reset circuit operates as a trigger for the master clock. the master clock should be input even while executing a reset. 3. when using the on-chip clock generator (when a crystal resonator is connected to xtl_out or xtl_in pin), only 24.576 mhz can be selected for f mclk . when using a frequency other than 24.576 mhz, be sure to input an externally generated clock directly to the xtl_in pin. 90% 10% t rstl t rrst t mclk reset master clock
data sheet s15003ej6v0ds 48 pd63335 ac characteristics, serial command interface block (unless otherwise specified, dv dd = av dd = 3.3 v, dv ss = av ss = 0 v, t a = ? ? ? ? 40 to +85 c) parameter symbol conditions min. typ. max. unit msclk cycle t msclk 240 ?? ns msclk high-level width t msch 100 ?? ns msclk low-level width t mscl 100 ?? ns msclk rise time t mscr ?? 20 ns msclk fall time t mscf ?? 20 ns setup time from _______ reset to msclk t mscrst 8 ?? t mclk data i/o start time t mschd 8 ?? t mclk data setup time t msdsu 50 ?? ns data hold time t msdhd 50 ?? ns reset msclk msrdt, mswdt bit7 bit6 bit0 bit7 bit6 bit0 t mscrst t mscr t msch t mschd t mschd t msclk t mscf t mscl t msdhd t msdsu 10% 90% 90% 50%
data sheet s15003ej6v0ds 49 pd63335 ac characteristics, serial data interface block (unless otherwise specified, dv dd = av dd = 3.3 v, dv ss = av ss = 0 v, t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit bit_clk input signal cycle t bi during bit_clk input 325.5 ?? ns bit_clk input signal high-level width t bih during bit_clk input 100 ?? ns bit_clk input signal low-level width t bil during bit_clk input 100 ?? ns bit_clk output signal cycle note t bo during bit_clk output 325.5 ?? ns bit_clk output signal high-level width t boh during bit_clk output 125 ?? ns bit_clk output signal low-level width t bol during bit_clk output 125 ?? ns lrclk-bitclk setup time t lrisu during lrclk input 50 ?? ns lrclk-bitclk hold time t lrihd during lrclk input 50 ?? ns delay time from lrclk to so 1 t dsolri during lrclk input ?? 70 ns delay time from lrclk to so 2 t dlrbo during lrclk output ? 40 ? +65 ns delay time from bit_clk fall to so 1 t dsobi during bit_clk input ?? 70 ns bit_clk fall to so 2 t dsobo during bit_clk output ? 40 ? +65 ns si setup time t sisu 50 ?? ns si hold time t sihd 50 ?? ns note when the number of bit clocks per frame in the serial data format is set to 48 according to the internal bit_clk generator configuration, the bit_clk output signal duty factor is not constant; some variation of master clock cycle may occur. serial data i/o timing (bit_clk and lrclk input) lrclk (output) so si bit_clk (output) t boh t bol t bo t dlrbo t sisu t sihd t dsobo 90% 10%
data sheet s15003ej6v0ds 50 pd63335 serial data output timing (bit_clk and lrclk output) lrclk (input) so si bit_clk (input) t bih t bil t bi t dsolri t dsobi t lrihd t lrisu t sisu t sihd 90% 10%
data sheet s15003ej6v0ds 51 pd63335 4. application circuit example figure 4-1. application circuit example outr outl nc nc nc afilt2 nc afilt1 nc av ss1 av dd1 vref dv dd3 msrdt mswdt test2 test1 av ss2 msclk dacr nc av dd2 mono_out dacl 48 47 46 45 44 43 42 41 40 39 38 37 in5 in3l in3r in2r in1l in1_gnd in2l in1r mic1 in4l in4r mic2 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 32 31 30 33 29 28 26 25 27 dv dd1 xtl_in xtl_out si bit_clk dv ss2 dv ss1 so dv dd2 reset in6 lrclk 1 2 3 5 6 7 4 8 9 11 12 10 monaural input in3 input in2 input in1 input mic input in4 input serial command interface dac output monaural output remark : analog ground : digital ground f 4.7 f 4.7 f 4.7 f 4.7 f 0.1 f 4.7 f 4.7 f 4.7 f 0.1 f 0.1 f 4.7 f 4.7 f 4.7 f 4.7 f 4.7 f 4.7 f 4.7 f 4.7 f 4.7 f 4.7 f 4.7 f 4.7 f 4.7 f 4.7 47 k ? 47 k ? 47 k ? 47 k ? 47 k ? 47 k ? 47 k ? 47 k ? + 3.3 v + 3.3 v + 3.3 v + 3.3 v 24.576 mhz 270 pf 270 pf serial data interface stereo output (tantalum)
data sheet s15003ej6v0ds 52 pd63335 5. recommended land pattern refer to the figure below for details of power supply and ground line wiring and the placement of bypass capacitors on the board. it is recommended to place bypass capacitors as close as possible to pins by utilizing the underside of the board, or by some other means. figure 5-1. recommended land pattern dv ss1 f) : chip ceramic capacitor (0.1 digital gnd analog gnd r (0 ? ) dv ss2 dv dd2 av ss1 av dd1 av dd2 av ss2 remark caution f) : tantalum capacitor (4.7 r (0 ? ) : connect analog and digital gnd at one point immediately below or adjacent to the codec. dv dd3 dv dd1 1 4 7 9 26 25 48 42 38
data sheet s15003ej6v0ds 53 pd63335 6. package drawing s s n j detail of lead end r k m l p i s q g f m h 48-pin plastic tqfp (fine pitch) (7x7) note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 9.0 0.2 7.0 0.2 0.5 (t.p.) 0.75 j 9.0 0.2 k c 7.0 0.2 i 0.10 1.0 0.2 l 0.5 0.2 f 0.75 n p q 0.10 1.0 0.1 0.1 0.05 s48ga-50-9eu-2 s 1.27 max. h 0.22 + 0.05 ? 0.04 m 0.145 + 0.055 ? 0.045 r3 + 7 ? 3 36 37 24 48 1 13 12 25 cd a b
data sheet s15003ej6v0ds 54 pd63335 7. recommended soldering conditions the pd63335 should be soldered and mounted under the following recommended conditions. for details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales representative. table 6-1. surface mounting type soldering conditions ? pd63335ga-9eu: 48-pin plastic tqfp (fine pitch) (7 7) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: three times or less, exposure limit note : 3 days (after that, prebaking is necessary at 125 c for 10 hours) ir35-103-3 vsp package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: three times or less, exposure limit note : 3 days (after that, prebaking is necessary at 125 c for 10 hours) vp15-103-3 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? note the number of days for storage after the dry pack has been opened. storage conditions are 25 c and 65% rh max. caution do not use different soldering methods together (except for partial heating).
data sheet s15003ej6v0ds 55 pd63335 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd63335 m8e 00. 4 the information in this document is current as of february, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?


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